From 88cc8a00f4a7fc34003b961c572d5a78462dd682 Mon Sep 17 00:00:00 2001
From: Mounir IDRASSI <mounir.idrassi@idrix.fr>
Date: Tue, 4 Jul 2017 11:19:53 +0200
Subject: Windows: correctly handle SEH exceptions during self-tests in order
 to disable CPU extended features in such case.

---
 src/Crypto/cpu.c | 26 ++++++++++++++++++++++----
 src/Crypto/cpu.h | 45 +++++++++++++++++++--------------------------
 2 files changed, 41 insertions(+), 30 deletions(-)

(limited to 'src/Crypto')

diff --git a/src/Crypto/cpu.c b/src/Crypto/cpu.c
index 7ec5b988..69a7fcff 100644
--- a/src/Crypto/cpu.c
+++ b/src/Crypto/cpu.c
@@ -200,10 +200,10 @@ static uint64 xgetbv()
 #endif
 }
 
-int g_x86DetectionDone = 0;
-int g_hasISSE = 0, g_hasSSE2 = 0, g_hasSSSE3 = 0, g_hasMMX = 0, g_hasAESNI = 0, g_hasCLMUL = 0, g_isP4 = 0;
-int g_hasAVX = 0, g_hasAVX2 = 0, g_hasBMI2 = 0, g_hasSSE42 = 0, g_hasSSE41 = 0, g_isIntel = 0, g_isAMD = 0;
-uint32 g_cacheLineSize = CRYPTOPP_L1_CACHE_LINE_SIZE;
+volatile int g_x86DetectionDone = 0;
+volatile int g_hasISSE = 0, g_hasSSE2 = 0, g_hasSSSE3 = 0, g_hasMMX = 0, g_hasAESNI = 0, g_hasCLMUL = 0, g_isP4 = 0;
+volatile int g_hasAVX = 0, g_hasAVX2 = 0, g_hasBMI2 = 0, g_hasSSE42 = 0, g_hasSSE41 = 0, g_isIntel = 0, g_isAMD = 0;
+volatile uint32 g_cacheLineSize = CRYPTOPP_L1_CACHE_LINE_SIZE;
 
 VC_INLINE int IsIntel(const uint32 output[4])
 {
@@ -381,5 +381,23 @@ int is_aes_hw_cpu_supported ()
 	return bHasAESNI;
 }
 
+void DisableCPUExtendedFeatures ()
+{
+	g_hasSSE2 = 0;
+	g_hasISSE = 0;
+	g_hasMMX = 0;
+	g_hasSSE2 = 0;
+	g_hasISSE = 0;
+	g_hasMMX = 0;
+	g_hasAVX = 0;
+	g_hasAVX2 = 0;
+	g_hasBMI2 = 0;
+	g_hasSSE42 = 0;
+	g_hasSSE41 = 0;
+	g_hasSSSE3 = 0;
+	g_hasAESNI = 0;
+	g_hasCLMUL = 0;
+}
+
 #endif
 
diff --git a/src/Crypto/cpu.h b/src/Crypto/cpu.h
index 68041190..cddec05c 100644
--- a/src/Crypto/cpu.h
+++ b/src/Crypto/cpu.h
@@ -186,38 +186,31 @@ extern "C" {
 #define CRYPTOPP_CPUID_AVAILABLE
 
 // these should not be used directly
-extern int g_x86DetectionDone;
-extern int g_hasAVX;
-extern int g_hasAVX2;
-extern int g_hasBMI2;
-extern int g_hasSSE42;
-extern int g_hasSSE41;
-extern int g_hasSSSE3;
-extern int g_hasAESNI;
-extern int g_hasCLMUL;
-extern int g_isP4;
-extern int g_isIntel;
-extern int g_isAMD;
-extern uint32 g_cacheLineSize;
+extern volatile int g_x86DetectionDone;
+extern volatile int g_hasSSE2;
+extern volatile int g_hasISSE;
+extern volatile int g_hasMMX;
+extern volatile int g_hasAVX;
+extern volatile int g_hasAVX2;
+extern volatile int g_hasBMI2;
+extern volatile int g_hasSSE42;
+extern volatile int g_hasSSE41;
+extern volatile int g_hasSSSE3;
+extern volatile int g_hasAESNI;
+extern volatile int g_hasCLMUL;
+extern volatile int g_isP4;
+extern volatile int g_isIntel;
+extern volatile int g_isAMD;
+extern volatile uint32 g_cacheLineSize;
 void DetectX86Features(); // must be called at the start of the program/driver
 int CpuId(uint32 input, uint32 *output);
-
-#if CRYPTOPP_BOOL_X64
-#define HasSSE2()	1
-#define HasISSE()	1
-#define HasMMX()	1
-#else
-
-extern int g_hasSSE2;
-extern int g_hasISSE;
-extern int g_hasMMX;
+// disable all CPU extended features (e.g. SSE, AVX, AES) that may have
+// been enabled by DetectX86Features.
+void DisableCPUExtendedFeatures (); 
 
 #define HasSSE2()	g_hasSSE2
 #define HasISSE()	g_hasISSE
 #define HasMMX()	g_hasMMX
-
-#endif
-
 #define HasSSE42() g_hasSSE42
 #define HasSSE41() g_hasSSE41
 #define HasSAVX() g_hasAVX
-- 
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