From 6ae982cccf42a54cef60f5948aa46604859b4871 Mon Sep 17 00:00:00 2001 From: Mounir IDRASSI Date: Fri, 17 Jun 2016 14:16:57 +0200 Subject: Update intrinsic support and cpu detection. --- src/Crypto/cpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/Crypto/cpu.c') diff --git a/src/Crypto/cpu.c b/src/Crypto/cpu.c index 3de87069..5f3643de 100644 --- a/src/Crypto/cpu.c +++ b/src/Crypto/cpu.c @@ -12,10 +12,6 @@ #include #endif -#if CRYPTOPP_BOOL_SSE2_INTRINSICS_AVAILABLE -#include -#endif - #ifdef CRYPTOPP_CPUID_AVAILABLE #if _MSC_VER >= 1400 && CRYPTOPP_BOOL_X64 @@ -165,6 +161,7 @@ static int TrySSE2() int g_x86DetectionDone = 0; int g_hasISSE = 0, g_hasSSE2 = 0, g_hasSSSE3 = 0, g_hasMMX = 0, g_hasAESNI = 0, g_hasCLMUL = 0, g_isP4 = 0; +int g_hasAVX = 0, g_hasSSE42 = 0, g_hasSSE41 = 0; uint32 g_cacheLineSize = CRYPTOPP_L1_CACHE_LINE_SIZE; VC_INLINE int IsIntel(const uint32 output[4]) @@ -194,6 +191,9 @@ void DetectX86Features() g_hasMMX = (cpuid1[3] & (1 << 23)) != 0; if ((cpuid1[3] & (1 << 26)) != 0) g_hasSSE2 = TrySSE2(); + g_hasAVX = g_hasSSE2 && (cpuid1[2] & (1 << 28)); + g_hasSSE42 = g_hasSSE2 && (cpuid1[2] & (1 << 20)); + g_hasSSE41 = g_hasSSE2 && (cpuid1[2] & (1 << 19)); g_hasSSSE3 = g_hasSSE2 && (cpuid1[2] & (1<<9)); g_hasAESNI = g_hasSSE2 && (cpuid1[2] & (1<<25)); g_hasCLMUL = g_hasSSE2 && (cpuid1[2] & (1<<1)); -- cgit v1.2.3